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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-50105-2E
MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
8M (x 8/x 16) FLASH MEMORY & 2M (x 8) STATIC RAM
MB84VA2002-10/MB84VA2003-10
s FEATURES
* Power supply voltage of 2.7 to 3.6 V * High performance 100 ns maximum access time * Operating Temperature -20 to +85C -- FLASH MEMORY * Minimum 100,000 write/erase cycles * Sector erase architecture One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes. Any combination of sectors can be concurrently erased. Also supports full chip erase. * Boot Code Sector Architecture MB84VA2002: Top sector MB84VA2003: Bottom sector * Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector * Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Ready-Busy output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. * Low VCC write inhibit 2.5 V * Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device * Please refer to "MBM29LV800TA/BA" data sheet in detailed function -- SRAM * Power dissipation Operating : 35 mA max. Standby : 50 A max. * Power down features using CE1s and CE2s * Data retention supply voltage: 2.0 V to 3.6 V
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
MB84VA2002-10/MB84VA2003-10
s BLOCK DIAGRAM
VCCf A0 to A18 A0 to A18 A-1 RESET CEf BYTE 8 M bit Flash Memory VSS
RY/BY DQ8 to DQ15
DQ0 to DQ7 VCCs A0 to A16 VSS
SA WE OE CE1s CE2s
2 M bit Static RAM
s EXAMPLE OF CONNECTION WITH CHIPSET
VCC
A[0:19]
A[1:19] A0
A[0:18] SA
VCCf BYTE RESET
ROM_CS/ RAM_CS/ Battery Backup Control BATTERY BACKUP HWR/ LWR/ RD/ D[0:15] D[0:15] CHIPSET
CEf CE1s
RY/BY
VCCs CE2s
WE OE
DQ[0:15] MB84VA2002/3
2
MB84VA2002-10/MB84VA2003-10
s PIN ASSIGNMENTS
(Top View) A
6 5 4 3 2 1 CE1s A10 OE A11 A13 WE
B
VSS DQ5 DQ7 A8 A17 VCCs
C
DQ1 DQ2 DQ4 A5 SA* A16
D
A1 A0 DQ0 DQ8 CEf VSS
E
A2 A3 A6 DQ3 DQ10 DQ9
F
A4 A7 A18 DQ12 VCCf DQ11
G
CE2s RY/BY RESET A12 DQ6 DQ13
H
A9 A14 A15 BYTE DQ15/A-1 DQ14
*: A17 for SRAM Table 1 Pin Configuration
Pin A0 to A16 A-1, A17 to A18 SA DQ0 to DQ7 DQ8 to DQ15 CEf CE1s CE2s OE WE RY/BY BYTE RESET N.C. VSS VCCf VCCs
Function Address Inputs (Common) Address Input (Flash) Address Input (SRAM) Data Inputs/Outputs (Common) Data Inputs/Outputs (Flash) Chip Enable (Flash) Chip Enable (SRAM) Chip Enable (SRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Outputs (Flash) Selects 8-bit or 16-bit mode (Flash) Hardware Reset Pin/Sector Protection Unlock (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (SRAM)
Input/ Output I I I I/O I/O I I I I I O I I -- Power Power Power
3
MB84VA2002-10/MB84VA2003-10
s PRODUCT LINE UP
Flash Memory Ordering Part No. VCC = 3.0 V
+0.6 V -0.3 V
SRAM
MB84VA2002-10/MB84VA2003-10 100 100 40 100 100 50
Max. Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns)
s BUS OPERATIONS
Table 2 User Bus Operations (BYTE=VIL) Operation (1), (3) Full Standby Output Disable Read from Flash (2) Write to Flash Read from SRAM Write to SRAM Flash Hardware Reset CEf H X L L H H X CE1s H X X H X H X L L H X CE2s X L X X L X L H H X L OE X H L H L X X WE X H H L H L X DQ0 to DQ7 DQ8 to DQ15 HIGH-Z HIGH-Z DOUT DIN DOUT DIN HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z RESET H H H H H H L
Table 3 User Bus Operations (BYTE=VIH) Operation (1), (3) Full Standby Output Disable Read from Flash (2) CEf H X L CE1s H X X H X H X L L H X CE2s X L X X L X L H H X L OE X H L WE X H H DQ0 to DQ7 DQ8 to DQ15 HIGH-Z HIGH-Z DOUT HIGH-Z HIGH-Z DOUT RESET H H H
Write to Flash Read from SRAM Write to SRAM Flash Hardware Reset
L H H X
H L X X
L H L X
DIN DOUT DIN HIGH-Z
DIN HIGH-Z HIGH-Z HIGH-Z
H H H L
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels. Notes: 1. Other operations except for indicated this column are inhibited. 2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 4. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. 4
MB84VA2002-10/MB84VA2003-10
s FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
* One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes. * Individual-sector, multiple-sector, or bulk-erase capability.
(x8) FFFFFH 16K byte FC000H 8K byte FA000H 8K byte F8000H 32K byte F0000H 64K byte E0000H 64K byte D0000H 64K byte C0000H 64K byte B0000H 64K byte A0000H 64K byte 90000H 64K byte 80000H 64K byte 70000H 64K byte 60000H 64K byte 50000H 64K byte 40000H 64K byte 30000H 64K byte 20000H 64K byte 10000H 64K byte 00000H MB84VA2002 Sector Architecture
(x16) 7FFFFH 64K byte 7E000H 64K byte 7D000H 64K byte 7C000H 64K byte 78000H 64K byte 70000H 64K byte 68000H 64K byte 60000H 64K byte 58000H 64K byte 50000H 64K byte 48000H 64K byte 40000H 64K byte 38000H 64K byte 30000H 64K byte 28000H 64K byte 20000H 32K byte 18000H 8K byte 10000H 8K byte 08000H 16K byte 00000H
(x8) FFFFFH F0000H E0000H D0000H C0000H B0000H A0000H 90000H 80000H 70000H 60000H 50000H 40000H 30000H 20000H 10000H 08000H 06000H 04000H 00000H MB84VA2003 Sector Architecture
(x16) 7FFFFH 78000H 70000H 68000H 60000H 58000H 50000H 48000H 40000H 38000H 30000H 28000H 20000H 18000H 10000H 08000H 04000H 03000H 02000H 00000H
5
MB84VA2002-10/MB84VA2003-10
Table 4 Sector Address Tables (MB84VA2002) Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 A14 X X X X X X X X X X X X X X X 0 1 1 1 A13 X X X X X X X X X X X X X X X X 0 0 1 A12 X X X X X X X X X X X X X X X X 0 1 X Address Range (x8) 00000H to 0FFFFH 10000H to 1FFFFH 20000H to 2FFFFH 30000H to 3FFFFH 40000H to 4FFFFH 50000H to 5FFFFH 60000H to 6FFFFH 70000H to 7FFFFH 80000H to 8FFFFH 90000H to 9FFFFH A0000H to AFFFFH B0000H to BFFFFH C0000H to CFFFFH D0000H to DFFFFH E0000H to EFFFFH F0000H to F7FFFH F8000H to F9FFFH FA000H to FBFFFH FC000H to FFFFFH Address Range (x16) 00000H to 07FFFH 08000H to 0FFFFH 10000H to 17FFFH 18000H to 1FFFFH 20000H to 27FFFH 28000H to 2FFFFH 30000H to 37FFFH 38000H to 3FFFFH 40000H to 47FFFH 48000H to 4FFFFH 50000H to 57FFFH 58000H to 5FFFFH 60000H to 67FFFH 68000H to 6FFFFH 70000H to 77FFFH 78000H to 7BFFFH 7C000H to 7CFFFH 7D000H to 7DFFFH 7E000H to 7FFFFH
6
MB84VA2002-10/MB84VA2003-10
Table 5 Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 A18 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Sector Address Tables (MB84VA2003) A14 0 0 0 1 X X X X X X X X X X X X X X X A13 0 1 1 X X X X X X X X X X X X X X X X A12 X 0 1 X X X X X X X X X X X X X X X X Address Range (x8) 00000H to 03FFFH 04000H to 05FFFH 06000H to 07FFFH 08000H to 0FFFFH 10000H to 1FFFFH 20000H to 2FFFFH 30000H to 3FFFFH 40000H to 4FFFFH 50000H to 5FFFFH 60000H to 6FFFFH 70000H to 7FFFFH 80000H to 8FFFFH 90000H to 9FFFFH A0000H to AFFFFH B0000H to BFFFFH C0000H to CFFFFH D0000H to DFFFFH E0000H to EFFFFH F0000H to FFFFFH Address Range (x16) 00000H to 01FFFH 02000H to 02FFFH 03000H to 03FFFH 04000H to 07FFFH 08000H to 0FFFFH 10000H to 17FFFH 18000H to 1FFFFH 20000H to 27FFFH 28000H to 2FFFFH 30000H to 37FFFH 38000H to 3FFFFH 40000H to 47FFFH 48000H to 4FFFFH 50000H to 57FFFH 58000H to 5FFFFH 60000H to 67FFFH 68000H to 6FFFFH 70000H to 77FFFH 78000H to 7FFFFH
7
MB84VA2002-10/MB84VA2003-10
Table 6. 1 Flash Memory Autoselect Codes Type Manufacturer's Code Byte MB84VA2002 Word Device Code Byte MB84VA2003 Word VIL VIL VIH X 225BH VIL 5BH VIL VIL VIH X 22DAH A6 VIL A1 VIL A0 VIL A-1*1 VIL VIL Code (HEX) 04H DAH
*1: A-1 is for Byte mode. Table 6. 2 Expanded Autoselect Code Table Type Manufacturer's Code MB84VA2002 (B) (W) MB84VA2003 (B) (W)
Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 1
04H A-1/0 DAH 22DAH 5BH 225BH A-1 0 A-1 0
Device Code
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 1 0 0 0 1 0 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 1 0 0 0 1 0
(B): Byte mode (W): Word mode
8
MB84VA2002-10/MB84VA2003-10
Table 7 Command Sequence Read/ Reset Read/ Reset
Bus Write Cycles Req'd
Flash Memory Command Definitions Second Bus Third Bus Write Cycle Write Cycle
First Bus Write Cycle Addr. XXXH
Fourth Bus Sixth Bus Fifth Bus Read/Write Write Cycle Write Cycle Cycle Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data F0H -- -- -- -- -- -- -- -- -- --
word 1 Byte word 3 Byte word Autoselect 3 Byte word Program 4 Byte word Chip 6 Erase Byte word Sector 6 Erase Byte Sector Erase Suspend Sector Erase Resume word Set to 3 Fast Mode Byte Fast word Program 2 Byte (Note) Reset word from Fast 2 Mode Byte Extended word Sector 4 Byte Protect
555H 2AAH 555H AAH 55H F0H RA RD -- -- -- -- AAAH 555H AAAH 555H 2AAH 555H AAH 55H 90H -- -- -- -- -- -- AAAH 555H AAAH 555H 2AAH 555H AAH 55H A0H PA PD -- -- -- -- AAAH 555H AAAH 555H 2AAH 555H 555H 2AAH 555H AAH 55H 80H AAH 55H 10H AAAH 555H AAAH AAAH 555H AAAH 555H 2AAH 555H 555H 2AAH AAH 55H 80H AAH 55H SA 30H AAAH 555H AAAH AAAH 555H Erase can be suspended during sector erase with Addr ("H" or "L"). Data (B0H) Erase can be resumed after suspend with Addr ("H" or "L"). Data (30H) 555H 2AAH 555H AAH 55H 20H -- -- -- -- -- -- AAAH 555H AAAH XXXH A0H PA PD -- -- -- -- -- -- -- -- XXXH XXXH XXXH 90H F0H -- -- -- -- -- -- -- -- XXXH XXXH XXXH 60H SPA 60H SPA 40H SPA SD -- -- -- --
Address bits A11 to A20 = X = "H" or "L" for all address commands except for Program Address (PA) and Sector Address (SA). Bus operations are defined in Table 2. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. RA =Address of the memory location to be read. PA =Address of the memory location to be programmed. Addresses are latched on the falling edge of the write pulse. SA =Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, and A13 will uniquely select any sector. RD =Data read from location RA during read operation. PD =Data to be programmed at location PA. SPA =Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0). SD =Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected sector addresses. Note:This command is valid while Fast Mode.
9
MB84VA2002-10/MB84VA2003-10
s ABSOLUTE MAXIMUM RATINGS
Storage Temperature .................................................................................................. -55C to +125C Ambient Temperature with Power Applied .................................................................. -25C to +85C Voltage with Respect to Ground All pins (Note) .......................................................... -0.3 V to VCCf +0.5 V -0.3 V to VCCs +0.5 V VCCf/VCCs Supply (Note) .............................................................................................. -0.3 V to +4.6 V Note: Minimum DC voltage on input or I/O pins are -0.5 V. During voltage transitions, inputs may negativeovershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are VCCf +0.5 V or VCCs +0.5 V. During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING RANGES
Commercial Devices Ambient Temperature (TA) .........................................................................-20C to +85C VCCf/VCCs Supply Voltages.........................................................................+2.7 V to +3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
10
MB84VA2002-10/MB84VA2003-10
s DC CHARACTERISTICS
Parameter Symbol
Parameter Description Input Leakage Current Output Leakage Current
Test Conditions -- -- Byte tCYCLE = 10 MHz
Min. -1.0 -1.0 -- -- -- -- -- -- -- -- -- -- -- --
Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- 1.5 -- 1 -- -- -- -- -- -- --
Max. +1.0 +1.0 22 25 12 15 35 40 12 35 6 5 5 2 2.5 55 3 60 2 5 50 0.6
VCC+0.3*
Unit A A
ILI ILO
ICC1f
VCCf = VCC Flash VCC Active Current Max., CEf = VIL (Read) OE = VIH
Word Byte Word
mA
tCYCLE = 5 MHz
ICC2f ICC1s
Flash VCC Active Current VCCf = VCC Max., CEf = VIL, OE = VIH (Program/Erase) SRAM VCC Active Current SRAM VCC Active Current Flash VCC Standby Current Flash VCC Standby Current (RESET) SRAM VCC Standby Current VCCs = VCC Max., CE1s = VIL, CE2s = VIH CE1s = 0.2 V, CE2s = VCCs - 0.2 V, WE = VCCs - 0.2 V tCYCLE =10 MHz tCYCLE = 1 MHz tCYCLE = 10 MHz tCYCLE = 1 MHz
mA mA mA mA mA A A mA A A A A A A A V V V V V
ICC2s ISB1f ISB2f ISB1s
VCCf = VCC Max., CEf = VCCf 0.3 V RESET = VCCf 0.3 V VCCf = VCC Max., RESET = VSS 0.3 V CE1s = VIH or CE2s = VIL VCCs = 3.0 V 10% VCCs = 3.3 V CE1s = VCC - 0.2 V or CE2s 0.3 V = 0.2 V VCCs = 3.0 V TA = 25C TA = -20 to +85C TA = 25C TA = -20 to +85C TA = 25C TA = -20 to +40C TA = -20 to +85C
-- -- -- -- -- -- -- -0.3 2.2 --
VCC - 0.5
ISB2s**
SRAM VCC Standby Current
VIL VIH VOL VOH VLKO
Input Low Level Input High Level Output Low Voltage Level Output High Voltage Level Flash Low VCC Lock-Out Voltage
-- -- IOL = 2.1 mA, VCCf = VCCs = VCC Min. IOH = -500 A, VCCf = VCCs = VCC Min. --
0.4 -- 2.5
2.3
* : VCC indicate lower of VCCf or VCCs ** :During standby mode with CE1s = VCCS - 0.2 V, CE2s should be CE2s < 0.2V or CE2s > VCCS - 0.2V 11
MB84VA2002-10/MB84VA2003-10
s AC CHARACTERISTICS
* CE Timing Parameter Symbols JEDEC -- Standard tCCR CE Recover Time -- Min. 0 ns
Description
Test Setup
-10
Unit
* Timing Diagram for alternating SRAM to Flash
CEf
tCCR
tCCR
CE1s
tCCR
tCCR
CE2s
* Read Only Operations Characteristics (Flash) Parameter Symbols JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX -- -- Standard tRC tACC tCEf tOE tDF tDF tOH tREADY tELFL tELFH Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Addresses, CEf or OE, Whichever Occurs First RESET Pin Low to Read Mode CE or BYTE Switching Low or High -- CEf = VIL OE = VIL OE = VIL -- -- -- -- -- -- Test Setup -10 (Note) Min. 100 -- -- -- -- -- 0 -- -- Max. -- 100 100 40 30 30 -- 20 5 ns ns ns ns ns ns ns s ns
Description
Unit
Note: Test Conditions-Output Load: 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level Input: 1.5 V Output: 1.5 V 12
MB84VA2002-10/MB84VA2003-10
* Read Cycle (Flash)
tRC
Addresses Stable
ADDRESSES tACC
CEf
tOE tDF
OE
tOEH
WE
tCE
DQ
HIGH-Z
Output Valid
HIGH-Z
tRC ADDRESSES tACC tRH
Addresses Stable
RESET
tOH
DQ
HIGH-Z
Output Valid
13
MB84VA2002-10/MB84VA2003-10
* Erase/Program Operations (Flash) Parameter Symbols JEDEC tAVAV tAVWL tAVEL tWLAX tELAX tDVWH tWHDX -- -- tGHEL tGHWL tWLEL tELWL tEHWH tWHEH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 -- -- -- -- -- -- -- -- -- -- Standard tWC tAS tAS tAH tAH tDS tDH tOES tOEH tGHEL tGHWL tWS tCS tWH tCH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVLHT tVIDR tRB tRP tRH tEOE tBUSY tFLQZ tFLQV Write Cycle Time Address Setup Time (WE to Addr.) Address Setup Time (CEf to Addr.) Address Hold Time (WE to Addr.) Address Hold Time (CEf to Addr.) Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Toggle and Data Polling Description -10 Min. 100 0 0 50 50 50 0 0 0 10 0 0 0 0 0 0 50 50 30 30 -- -- -- 50 4 500 0 500 200 -- -- -- 30 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8 1 -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15 -- -- -- -- -- -- 100 90 30 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s sec sec s s ns ns ns ns ns ns ns ns
Read Recover Time Before Write (OE to CEf) Read Recover Time Before Write (OE to WE) WE Setup Time (CEf to WE) CEf Setup Time (WE to CEf) WE Hold Time (CEf to WE) CEf Hold Time (WE to CEf) Write Pulse Width CEf Pulse Width Write Pulse Width High CEf Pulse Width High Byte Programming Operation Sector Erase Operation (Note 1) VCCf Setup Time Voltage Transition Time (Note 2) Rise Time to VID (Note 2) Recover Time from RY/BY RESET Pulse Width RESET Hold Time Before Read Delay Time from Embedded Output Enable Program/Erase Valid to RY/BY Delay BYTE Switching Low to Output High-Z BYTE Switching High to Output Active
Note : 1. This does not include the preprogramming time. 2. This timing is for Sector Protection Operation. 14
MB84VA2002-10/MB84VA2003-10
* Write Cycle (WE control) (Flash)
3rd Bus Cycle
ADDRESSES 555H tWC tAS PA tAH
Data Polling
PA tRC
CEf
tCS tCH tCO
OE
tGHWL tWP tWPH tWHWH1 tFOE
WE
tDS tDH tOH
DQ
A0H
PD
DQ7
DOUT
DOUT
Notes: 1. 2. 3. 4. 5. 6.
PA is address of the memory location to be programmed. PD is data to be programmed at byte address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence These waveforms are for the x16 mode. The addresses differ from x8 mode.
15
MB84VA2002-10/MB84VA2003-10
* Write Cycle (CEf control) (Flash)
3rd Bus Cycle ADDRESSES 555H tWC tAS PA tAH
Data Polling PA
WE
tWS tWH
OE
tGHEL tCP tCPH tWHWH1
CEf
tDS tDH
DQ
A0H
PD
DQ7
DOUT
Notes: 1. 2. 3. 4. 5. 6.
PA is address of the memory location to be programmed. PD is data to be programmed at byte address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence These waveforms are for the x16 mode. The addresses differ from x8 mode.
16
MB84VA2002-10/MB84VA2003-10
* AC Waveforms Chip/Sector Erase Operations (Flash)
ADDRESSES
555H tWC
2AAH tAS tAH
555H
555H
2AAH
SA*1
CEf
tCS tCH
OE
tGHWL tWP tWPH
WE
tDS tDH AAH 55H 80H AAH 55H 30H for Sector Erase 10H/ 30H
DQ
tVCS
VCC
Notes: 1. SA is the sector address for Sector Erase. Addresses = 555H forChip Erase. 2. These waveforms are for the x16 mode. The addresses differ from x8 mode.
17
MB84VA2002-10/MB84VA2003-10
* AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
CEf
tCH
tFOE
tOD
OE
tOEH
WE
tCO
* DQ7
Data In DQ7 DQ7 = Valid Data
High-Z
tWHWH1 or 2
High-Z
DQ (DQ0 to DQ6)
Data In
DQ0 to DQ6 = Invalid
DQ0 to DQ6 Valid Data
tEOE
*DQ7 = Valid Data (The device has completed the Embedded operation.) * AC Waveforms for Taggle Bit during Embedded Algorithm Operations (Flash)
CEf
tOEH
WE
tOES
OE
*
DQ6
Data In DQ6 = Toggle DQ6 = Toggle DQ6 = Stop Toggling tEOE
DQ0 to DQ7 Data Valid
*DQ6 = Stops toggling. (The device has completed the Embedded operation.)
18
MB84VA2002-10/MB84VA2003-10
* RY/BY Timing Diagram during Write/Erase Operations (Flash)
CEf
The rising edge of the last WE signal
WE
Entire programming or erase operations
RY/BY
tBUSY
* RESET, RY/BY Timing Diagram (Flash)
WE
RESET
tRP tRB
RY/BY
tREADY
* Timing Diagram for Word Mode Configuration (Flash)
CE
BYTE
Data Output (DQ0 to DQ7) tELFH tFHQV A-1 DQ15 Data Output (DQ0 to DQ14)
DQ0 to DQ14
DQ15/A-1
19
MB84VA2002-10/MB84VA2003-10
* Timing Diagram for Byte Mode Configuration (Flash)
CE
BYTE
tELFL
DQ0 to DQ14
Data Output (DQ0 to DQ14)
Data Output (DQ0 to DQ7)
DQ15/A-1
DQ15 tFLQZ
A-1
* BYTE Timing Diagram for Write Operations (Flash)
The falling edge of the last WE signal
CE or WE
BYTE
tSET (tAS)
Input Valid
tHOLD (tAH)
* Temporary Sector Unprotection (Flash)
VCC tVCS VID 3V RESET CE
tVIDR tVLHT
3V
WE
tVLHT RY/BY
Program or Erase Command Sequence
tVLHT
Unprotection period
20
MB84VA2002-10/MB84VA2003-10
* Extended Sector Protection (Flash)
VCC tVCS
RESET tVIDR
tVLHT
Add
SPAX
SPAX
SPAY
A0
A1
A6
CE
OE TIME-OUT
WE
Data
60H
60H
40H tOE
01H
60H
SPAX : Sector Address to be protected SPAY : Next Sector Address to be protected TIME-OUT : Time-Out window = 150 s (min)
21
MB84VA2002-10/MB84VA2003-10
* Read Cycle (SRAM) Parameter Symbol tRC tAA tCO1 tCO2 tOE tCOE tOEE tOD tODO tOH Parameter Description Read Cycle Time Address Access Time Chip Enable (CE1s) Access Time Chip Enable (CE2s) Access Time Output Enable Access Time Chip Enable (CE1s Low and CE2s High) to Output Active Output Enable Low to Output Active Chip Enable (CE1s High or CE2s Low) to Output High-Z Output Enable High to Output High-Z Output Data Hold Time Min. 100 -- -- -- -- 5 0 -- -- 10 Max. -- 100 100 100 50 -- -- 40 40 -- Unit ns ns ns ns ns ns ns ns ns ns
* Read Cycle (Note 1) (SRAM)
tRC ADDRESSES tAA tCO1 CE1s tCOE tCO2 CE2s tOD tOE OE tOEE tCOE DQ VALID DATA OUT tODO tOD tOH
Note: 1. WE remains HIGH for the read cycle.
22
MB84VA2002-10/MB84VA2003-10
* Write Cycle (SRAM) Parameter Description Write Cycle Time Write Pulse Width Chip Enable to End of Write Address Setup Time Write Recovery Time WE Low to Output High-Z WE High to Output Active Data Setup Time Data Hold Time Min. 100 60 80 0 0 -- 0 40 0 Max. -- -- -- -- -- 40 -- -- -- Unit ns ns ns ns ns ns ns ns ns Parameter Symbol tWC tWP tCW tAS tWR tODW tOEW tDS tDH
* Write Cycle (Note 4) (WE control) (SRAM)
tWC ADDRESSES tAS tWP tWR
WE
tCW CE1s
CE2s
tCW tODW
tOEW
DOUT
Note 2 tDS tDH
Note 3
DIN
Note 5
VALID DATA IN
Note 5
Notes: 2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output will remain at high impedance. 3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output will remain at high impedance. 4. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied.
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MB84VA2002-10/MB84VA2003-10
* Write Cycle (Note 4) (CE1s control) (SRAM)
tWC ADDRESSES tAS tWP tWR
WE
tCW CE1s
CE2s
tCW tCOE
tODW
DOUT tDS tDH
DIN
Note 5
VALID DATA IN
Note 5
Notes: 2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output will remain at high impedance. 3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output will remain at high impedance. 4. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied.
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MB84VA2002-10/MB84VA2003-10
* Write Cycle (Note 4) (CE2s Control) (SRAM)
tWC ADDRESSES tAS tWP tWR
WE
tCW CE1s
CE2s tCW tCOE DOUT tDS tDH tODW
DIN
Note 5
VALID DATA IN
Note 5
Notes: 2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output will remain at high impedance. 3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output will remain at high impedance. 4. If OE is HIGH during the write cycle, the outputs will remain at high impedance. 5. Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied.
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MB84VA2002-10/MB84VA2003-10
s ERASE AND PROGRAMMING PERFORMANCE (Flash)
Limits Parameter Min. Sector Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycle -- -- -- 100,000 Typ. 1 8 12 -- Max. 15 3,600 T.B.D -- sec s sec cycles Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead Unit Comment
s DATA RETENTION CHARACTERISTICS (SRAM)
Parameter Symbol VDH IDDS2 tCDR tR Parameter Description Data Retention Supply Voltage VDH = 3.0 V Standby Current VDH = 3.6 V Chip Deselect to Data Retention Mode Time Recovery Time -- 0 5 -- -- -- 60 -- -- Min. 2.0 -- Typ. -- -- Max. 3.6 50* Unit V A A ns ms
* : 5 A (Max.) at TA = -20C to +40C * CE1s Controlled Data Retention Mode (Note 1)
VCCs
DATA RETENTION MODE
2.7 V
See Note 2 VIH VCCS -0.2 V tCDR
See Note 2
CE1s
tR
GND
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MB84VA2002-10/MB84VA2003-10
* CE2s Controlled Data Retention Mode (Note 3)
VCCs
DATA RETENTION MODE
2.7 V VIH CE2s tCDR tR
VIL
0.2 V
GND
Notes: 1. In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs-0.2V or Vss to 0.2V during data retention mode. Other input and input/output pins can be used between -0.3V to Vccs+0.3V. 2. When CE1s is operating at the VIH min. level (2.2 V), the standby current is given by ISB1s during the transition of VCCs from 3.6 to 2.2 V. 3. In CE2s controlled data retention mode, input and input/output pins can be used between between -0.3V to Vccs+0.3V.
s PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ. T.B.D T.B.D T.B.D Max. T.B.D T.B.D T.B.D Unit pF pF pF
Note: Test conditions TA = 25C, f = 1.0 MHz
s HANDRING OF PACKAGE
Please handle this package carefully since the sides of packages are right angle.
s CAUTION
1.)The high voltage (VID) can not apply to address pins and control pins except RESET. Therefore, it can not use autoselect and sector protect function by applying the high voltage (VID) to specific pins. 2.)For the sector protection, since the high voltage (VID) can be applied to the RESET, it can be protected the sector useing "Extended sector protect" command.
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MB84VA2002-10/MB84VA2003-10
s PACKAGE
48-pin plastic FBGA
(BGA-48P-M06)
s PACKAGE DIMENSIONS
48-pin plastic BGA (BGA-48P-M06) Note: The actual shape of coners may differ from the dimension.
11.000.15(.433.006)
1.400.20 (.055.008) 0.300.10 (.012.004)
7.000.15(.276.006)
10.000.15 (.394.006)
O0.400.10 (O.016.004)
5.000.15 (.197.006)
0.15(.006) 1st PIN
INDEX
1.000.15 (.039.006)
INDEX
C
1998 FUJITSU LIMITED MCM-M001-2-3
Dimension in mm (inches).
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MB84VA2002-10/MB84VA2003-10
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9805 (c) FUJITSU LIMITED Printed in Japan
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